CMOS interface circuits for reading and writing memristor crossbar array

Author

Qureshi, Muhammad Shakeel ; Pickett, Matthew ; Miao, Feng ; Strachan, John Paul

Author_Institution

Inf. Quantum Syst. Lab., Hewlett Packard Labs., Palo Alto, CA, USA

fYear

2011

fDate

15-18 May 2011

Firstpage

2954

Lastpage

2957

Abstract

This paper describes CMOS interface circuits in 350nm 3.3V/5.0V TSMC process for memristor crossbar array. These circuits are applicable for non-volatile resistive memories. The architecture is targeted for low power and high speed applications. We have demonstrated sense amplifiers for reading the state of a memristor bit. Voltage divider and transimpedence amplifier is used for DC sensing while sigma delta approach is used for averaging. Current limiting write amplifier has also been designed for increasing the device endurance and reliability. Half select array architecture is used to minimize dc leakage current in the crossbar array.

Keywords

CMOS integrated circuits; amplifiers; integrated circuit reliability; low-power electronics; memristors; random-access storage; voltage dividers; CMOS interface circuits; DC sensing; TSMC process; half select array; high speed applications; low power applications; memristor crossbar array; nonvolatile resistive memories; reliability; sense amplifiers; sigma delta approach; size 350 nm; transimpedence amplifier; voltage 3.3 V; voltage 5.0 V; voltage divider; Arrays; CMOS integrated circuits; Driver circuits; Memristors; Sigma delta modulation; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5938211

Filename

5938211