A fault tolerant parallel-prefix adder for VLSI and FPGA design

A fault tolerant parallel-prefix adder can be implemented using a Kogge-Stone configuration due to the inherent redundancy in the carry-tree. While this design can be used to correct a fault in the carry-tree, no provision was made for fault detectability. This paper proposes utilizing a sparse Kogge-Stone adder that is capable of both fault detectability and fault correction. The sparse carry tree is complemented by several smaller ripple carry adders. Two additional ripple carry adders allow fault tolerance to be achieved. A triple-mode redundant ripple carry adder (TMR-RCA) is used as a point of reference. Synthesis and simulation for an FPGA platform are carried out. It is found that the TMR-RCA is still the best approach for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree over a ripple carry adder in a VLSI implementation makes this proposed approach attractive for ASIC designs.