DocumentCode
2010894
Title
Counting Dependence Predictors
Author
Roesner, Franziska ; Burger, Doug ; Keckler, Stephen W.
Author_Institution
Dept. of Comput. Sci., Univ. of Texas at Austin, Austin, TX
fYear
2008
fDate
21-25 June 2008
Firstpage
215
Lastpage
226
Abstract
Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To date, the most sophisticated dependence predictors, such as Store Sets, have been tightly coupled to the fetch and execution streams, requiring global knowledge of the in-flight stream of stores to synchronize loads with specific stores. This paper proposes a new dependence predictor design, called a Counting Dependence Predictor (CDP). The key feature of CDPs is that the prediction mechanism predicts some set of events for which a particular dynamic load should wait, which may include some number of matching stores. By waiting for local events only, this dependence predictor can work effectively in a distributed microarchitecture where centralized fetch and execution streams are infeasible or undesirable. We describe and evaluate a distributed Counting Dependence Predictor and protocol that achieves 92% of the performance of perfect memory disambiguation. It outperforms a load-wait table, similar to the Alpha 21264, by 11%. Idealized, centralized implementations of Store Sets and the Exclusive Collision Predictor, both of which would be difficult to implement in a distributed microarchitecture, achieve 97% and 94% of oracular performance, respectively.
Keywords
microprocessor chips; resource allocation; storage management; counting dependence predictors; distributed microarchitecture; load instructions; load-wait table; memory dependence prediction; memory disambiguation; store sets; Computer aided instruction; Computer architecture; Costs; Counting circuits; Delay; Microarchitecture; Microprocessors; Routing protocols; Tiles; Wire; dependence prediction; memory systems; multiprocessor and multicore architectures;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 2008. ISCA '08. 35th International Symposium on
Conference_Location
Beijing
ISSN
1063-6897
Print_ISBN
978-0-7695-3174-8
Type
conf
DOI
10.1109/ISCA.2008.6
Filename
4556728
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