DocumentCode
2011766
Title
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs
Author
Shi-Yu Huang ; Li-Ren Huang ; Kun-Han Tsai ; Wu-Tung Cheng
Author_Institution
Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2013
fDate
6-13 Sept. 2013
Firstpage
1
Lastpage
8
Abstract
Delay testing and characterization of interposer wires in a 2.5-D stacked IC is essential for yield learning and silicon debug. This paper addresses this problem by proposing a data analysis flow for perturbation-based oscillation test method to cope with the various wire-lengths of the interposer wires. With the proposed method, one can not only detect small delay faults but also characterize the delay across each fault-free interposer wire.
Keywords
data analysis; delays; fault diagnosis; integrated circuit testing; wires (electric); 2.5D stacked IC; data analysis flow; delay testing; fault-free interposer wire; perturbation-based oscillation test method; post-bond interposer wire characterization; silicon debug; small delay fault detection; wire-lengths; yield learning; Circuit faults; Delays; Inverters; Oscillators; Testing; Through-silicon vias; Wires; 2.5-D Stacked IC; Delay Testing; Delay characterization; Interposer Wire; Post-Bond IC;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference (ITC), 2013 IEEE International
Conference_Location
Anaheim, CA
ISSN
1089-3539
Type
conf
DOI
10.1109/TEST.2013.6651906
Filename
6651906
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