VLSI MAP decoder architectural analysis

Author

Elassal, Mahmoud ; Bayoumi, Magdy

Author_Institution

Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA

fYear

2004

fDate

13-15 Oct. 2004

Firstpage

292

Lastpage

297

Abstract

This paper presents an architectural analysis for MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.

Keywords

VLSI; field programmable gate arrays; iterative decoding; maximum likelihood decoding; turbo codes; ALAP schedule policy; FPGA implementation; VLSI MAP decoder; branch memory size minimization; branch metric operations; decoder hardware implementation; iterative decoding; maximum a posteriori decoding; power consumption minimization; trellis-time graph graphical representation; turbo coding; Communication standards; Computer architecture; Convolution; Energy consumption; Field programmable gate arrays; Hardware; Iterative algorithms; Iterative decoding; Processor scheduling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on

Print_ISBN

0-7803-8504-7

Type

conf

DOI

10.1109/SIPS.2004.1363065

Filename

1363065