Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects

In this paper, we point out the importance of considering sensitivity performances due to process variations and operating voltage conditions during the design process. We demonstrate that such considerations significantly decrease the read timing margin introduced by the traditional corner method. However, this implies using statistical design technique which is introduced herein. The memory considered is a 256 kb SRAM design in 90 nm technology node.