Raising the Level of Abstraction for the Timing Verification of System-on-Chips

This paper proposes a general system-level timing verification method for System-on-Chips (SoC). Experiments have been carried out on several synthetic benchmark SoCs. Delays at the various interconnects are extracted from the SDF file generated after place and route. A graph of interconnects and cores is generated for each SoC, with the extracted delays back annotated as weights. Algorithms have been presented that verifies the timing criteria at various check points in the circuit.