DocumentCode
2013707
Title
A rapid and scalable diagnosis scheme for BIST environments with a large number of scan chains
Author
Ghosh-Dastidar, Jayabrata ; Touba, Nur A.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
2000
fDate
2000
Firstpage
79
Lastpage
85
Abstract
This paper presents a rapid and scalable built-in-self-test (BIST) diagnosis scheme for handling BIST environments with a large number of scan chains. The problem of identifying which scan cells captured errors during the BIST session is formulated here as a search problem. A scheme for adding a small amount of additional hardware that provides the capability of performing very efficient search techniques to locate the error-capturing scan cells is proposed. The scheme can accurately diagnose any number of error-capturing scan cells. The error-capturing scan cells can be located in time complexity that is logarithmic in the total number of scan cells in the design using the proposed approach. The technique scales well for very large designs. The hardware overhead is logarithmic in the number of scan cells and linear in the number of scan chains
Keywords
automatic testing; boundary scan testing; built-in self test; computational complexity; design for testability; fault diagnosis; integrated circuit testing; production testing; BIST environments; error-capturing scan cells; hardware overhead; scalable diagnosis scheme; scan cells; scan chains; search problem; search techniques; time complexity; Built-in self-test; Circuit testing; Costs; Design for disassembly; Integrated circuit reliability; Manufacturing processes; Microwave integrated circuits; Postal services; Silicon; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location
Montreal, Que.
ISSN
1093-0167
Print_ISBN
0-7695-0613-5
Type
conf
DOI
10.1109/VTEST.2000.843830
Filename
843830
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