SIFAR: static test compaction for synchronous sequential circuits based on single fault restoration

Author

Lin, Xijiang ; Cheng, Wu-Tung ; Pomeranz, Irith ; Reddy, Sudhakar M.

Author_Institution

Mentor Graphics Corp., Wilsonville, OR, USA

fYear

2000

fDate

2000

Firstpage

205

Lastpage

212

Abstract

We propose a new approach for implementing static compaction procedures for synchronous sequential circuits. The procedures we consider belong to the class of procedures that generate the compacted test sequence through restoration of segments (or subsequences) of a given test sequence T. Under the proposed approach, each restored segment detects a single target fault chosen from the faults detected by T at one time unit. A novel parallel pattern simulator is developed for this purpose. Experimental results for benchmark circuits are included

Keywords

automatic test pattern generation; fault diagnosis; logic testing; sequential circuits; SIFAR; benchmark circuits; parallel pattern simulator; segment restoration; single fault restoration; static test compaction; subsequences; synchronous sequential circuits; test sequence; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Compaction; Electrical fault detection; Engines; Fault detection; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Conference_Location

Montreal, Que.

ISSN

1093-0167

Print_ISBN

0-7695-0613-5

Type

conf

DOI

10.1109/VTEST.2000.843847

Filename

843847