DocumentCode
2014177
Title
An effective defect-oriented BIST architecture for high-speed phase-locked loops
Author
Kim, Seongwon ; Soma, Mani ; Risbud, Dilip
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear
2000
fDate
2000
Firstpage
231
Lastpage
236
Abstract
We propose a new method of defect-oriented testing of PLL using charge-based frequency measurement BIST (CF-BIST) technique. As no test stimulus is required and the test output is pure digital, low-cost and practical implementation of on-chip BIST for a PLL is possible. Fault simulations using the 900 MHz PLL from National Semiconductor Corp. show higher fault coverage than previous test methods
Keywords
boundary scan testing; built-in self test; fault simulation; high-speed integrated circuits; integrated circuit testing; phase locked loops; 900 MHz; charge-based frequency measurement BIST; defect-oriented BIST architecture; fault coverage; fault simulations; high-speed phase-locked loops; test output; test stimulus; Area measurement; Built-in self-test; Charge pumps; Circuit faults; Circuit testing; Counting circuits; Frequency conversion; Phase locked loops; Voltage measurement; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location
Montreal, Que.
ISSN
1093-0167
Print_ISBN
0-7695-0613-5
Type
conf
DOI
10.1109/VTEST.2000.843850
Filename
843850
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