Systematic design of full adder-based architectures for convolution

The systematic design of full adder-based architectures for computing a 1-D circular convolution using the Residue Number System is introduced. The proposed architectures consist of three stages that exhibit regular and modular structure. Trade-offs between hardware complexity and speed are achieved by applying partitioning techniques to each stage. Through a recently developed multiplierless algorithm, the convolution is reduced to the computation of a series of squaring operations. Based on this fact, a general graph-based methodology for designing circuits that perform raising to the Nth power modulo m is presented.<>