Advance semiconductor package applied on high efficiency dual-mode DC-DC buck converter

This work analyzes the electrical performance for three different packaging types applied on power management IC (PMIC) using a high efficiency dual-mode DC-DC buck converter. A 600 mA with 93 % efficiency dual-mode DC-DC buck converter is designed and fabricated by TSMC 0.35-µm CMOS process. The chip area is smaller about 2.1 mm². The packaging parasitic effects of advanced single sided substrates (aS³ package) with wire-bond interconnect / copper pillar bump and fan-out wafer level chip scale package (fan-out WLP) are extracted from the layout drawings using the Ansys Q3D Extractor. A SPICE based circuit model of DC-DC buck converter is applied to determine the power dissipation. The power dissipation of the DC-DC buck converter implemented on aS³ package with wire-bond interconnect / copper pillar bump and fan-out WLP are 20 mW, 6 mW, and 5 mW, respectively. For high efficiency DC-DC buck converter application, aS³ package with copper pillar bump is applicable for medium pin count solutions and low cost packaging technology. Fan-out WLP is applicable for high pin count solutions with small-size and high performance.