FPGA implementation of a space-time trellis decoder

This paper describes the real-time implementation of a space-time trellis encoder and decoder using the Xilinx Virtex-4¿FX12 FPGA. The code uses a generator matrix designed for 4-state space-time trellis (STT) that uses Quadrature Phase Shift Keying (QPSK) modulation scheme. The decoding process was done using Maximum Likelihood (ML) through the Viterbi Algorithm. The results show that the STT decoder can successfully decipher the encoded symbols from the STT encoder and that it can fully recover the original data in the absence of noise. The data rate of the decoder was 6.25 Msymbols/s. It was shown that 14% of the logic elements in Virtex 4 FPGA were used in implementing an encoder-decoder system.