• DocumentCode
    2023925
  • Title

    High performance parallel packet Classification architecture with Popular Rule Caching

  • Author

    Gamage, Sahan ; Pasqual, Ajith

  • Author_Institution
    Dept. of Electron. & Telecommun. Eng., Univ. of Moratuwa, Moratuwa, Sri Lanka
  • fYear
    2012
  • fDate
    12-14 Dec. 2012
  • Firstpage
    52
  • Lastpage
    57
  • Abstract
    Packet Classification is the enabling function for many Internet functions like QoS and Security. In this paper we propose a Classification engine architecture which exploits parallelism to increase throughput. The architecture also make use of the Temporal locality observed in Internet traffic positively by employing Popular Rule Caching mechanism to increase the classification throughput. We also introduce Rule Splitting mechanism to increase the accuracy of the rule caching mechanism. Simulation results revealed that the architecture is capable of achieving a throughput of more than 200Gbps when lowest amount of temporal locality is present for worst case packet size of 40 bytes.
  • Keywords
    Internet; quality of service; Internet functions; Internet traffic; QoS; classification engine architecture; classification throughput; high performance parallel packet classification architecture; popular rule caching mechanism; rule splitting mechanism; temporal locality; worst case packet size; Clocks; Engines; Equations; Internet; Power demand; Registers; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networks (ICON), 2012 18th IEEE International Conference on
  • Conference_Location
    Singapore
  • ISSN
    1556-6463
  • Print_ISBN
    978-1-4673-4521-7
  • Type

    conf

  • DOI
    10.1109/ICON.2012.6506533
  • Filename
    6506533