A test solution for oxide thickness variations in the ATMEL TSTAC™ eFlash technology

Author

Mauroux, P.-D. ; Virazel, A. ; Bosio, A. ; Dilillo, L. ; Girard, P. ; Pravossoudovitch, S. ; Godard, B. ; Festes, G. ; Vachez, L.

Author_Institution

LIRMM, Univ. of Montpellier, Montpellier, France

fYear

2011

fDate

6-8 April 2011

Firstpage

1

Lastpage

6

Abstract

The embedded Flash (eFlash) technologies are based on the Floating Gate (FG) concept and can be subject to defects leading to retention and reliability problems. One of the most important aspects to guarantee high retention and reliability levels is the oxide thickness where the electric field is applied for charge injection and removal. In this paper, we analyze the impact of a defective oxide thickness on memory core cells built with the ATMEL TSTAC™ technology. We show how this variation of oxide thickness impacts the erase and write operations and consequently, the retention and the reliability of the memory. Then, we propose a test solution able to characterize and test the oxide thickness. This solution consists in adapting the inhibition voltage of non-selected bit lines during write operations.

Keywords

flash memories; reliability; ATMEL TSTA eFlash technology; FG concept; Floating Gate concept; memory reliability level; nonselected bit line; oxide thickness variation; test solution; Arrays; Electric fields; Nonvolatile memory; Programming; Reliability; SPICE; Transistors; NAND array; characterization and test; embedded Flash; oxide thickness; reliability; retention;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on

Conference_Location

Athens

Print_ISBN

978-1-61284-899-0

Type

conf

DOI

10.1109/DTIS.2011.5941431

Filename

5941431