Maximum current estimation in programmable logic arrays

Author

Bobba, S. ; Hajj, I.N.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1998

fDate

19-21 Feb 1998

Firstpage

301

Lastpage

306

Abstract

Programmable logic array (PLA) is a circuit realization for the two-level sum of products representation of a multi-output Boolean function. The current drawn by a PLA is input dependent and it makes the problem of estimating the maximum current intractable. Integrated circuit reliability and signal integrity are related to the maximum current drawn by the circuit. Hence, an estimate of the maximum current is required for the design of a reliable VLSI circuit. In this paper, we present an input pattern-independent algorithm to obtain the estimate of maximum and minimum currents drawn by a PLA over all possible input vectors. Experimental results on several benchmark circuits and comparisons with exhaustive simulations are also included in this paper

Keywords

Boolean functions; VLSI; integrated circuit design; integrated circuit reliability; logic CAD; programmable logic arrays; IC reliability; VLSI; benchmark circuits; current estimation; input dependent current; input pattern-independent algorithm; input vectors; multi-output Boolean function; programmable logic arrays; signal integrity; two-level sum of products representation; Boolean functions; Circuit simulation; Degradation; Electronic mail; Energy dissipation; Integrated circuit interconnections; Integrated circuit reliability; Logic circuits; Programmable logic arrays; Temperature; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Conference_Location

Lafayette, LA

ISSN

1066-1395

Print_ISBN

0-8186-8409-7

Type

conf

DOI

10.1109/GLSV.1998.665276

Filename

665276