The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in a Technology for Volume Semiconductor Manufacturing

Author

Berndlmaier, Zachary ; Winslow, Jonathan ; Desineni, Rao ; Blauberg, Alisa ; Chu, Benjamin

Author_Institution

IBM 300mm Semicond. Characterization Organ., Hopewell Junction, NY

fYear

2006

fDate

22-24 May 2006

Firstpage

405

Lastpage

410

Abstract

A method of communicating a unified pareto, we call "Grand Pareto", for technology-wide defects that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical failure analysis to create a single message for the process community to drive the yield improvement efforts. The methodology has been successfully deployed at IBM where it has been assisting in identifying key yield detractors for several high-end microprocessors in volume production

Keywords

Pareto analysis; integrated circuit yield; isolation technology; microprocessor chips; profitability; semiconductor device manufacture; Grand Pareto methodology; IBM; defect detection; fabrication facility; high-end microprocessors; isolation techniques; physical failure analysis; profitability limit; semiconductor manufacturing; technology-wide defects; unified pareto communication; volume production; yield detractors; yield improvement; Failure analysis; Inspection; Logic testing; Manufacturing; Microprocessors; Production facilities; Profitability; Semiconductor device manufacture; Vehicles; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

1-4244-0254-9

Type

conf

DOI

10.1109/ASMC.2006.1638792

Filename

1638792