Practical design for controlled impedance

Author

Canright, Robert E., Jr.

Author_Institution

Martin Marietta Electron. Orlando, FL, USA

fYear

1991

fDate

11-16 May 1991

Firstpage

370

Lastpage

377

Abstract

A novel method for designing controlled impedance transmission lines for high-speed digital systems is introduced. The method requires specification of the desired electrical performance, some device parameters, and the desired characteristic impedance (Z₀). By following this procedure, the minimum and maximum Z ₀ values that meet electrical performance and the useful tolerances on the nominal Z₀ are maximized. The value of the termination resistor that maximizes the tolerances on Z ₀ is also obtained. In the ideal case of transmission line termination, the termination resistor matches the line impedance. In the practical case, the optimum series termination resistor for high-speed digital systems is less than the nominal line impedance. The optimum parallel termination resistor will have a higher value than the nominal line impedance

Keywords

digital circuits; digital systems; impedance matching; packaging; transmission line theory; characteristic impedance; controlled impedance transmission lines; design method; high-speed digital systems; optimum parallel termination resistor; optimum series termination resistor; Dielectric substrates; Digital systems; Impedance; Manufacturing processes; Multichip modules; Reflection; Resistors; Transmission line theory; Transmission lines; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1991. Proceedings., 41st

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-0012-2

Type

conf

DOI

10.1109/ECTC.1991.163902

Filename

163902