Multi-bit flip-flop usage impact on physical synthesis

Reducing clock network power is an efficient way to reduce power consumption of the high-frequency ASICs since it accounts for a considerable amount of the dynamic chip power. Recently, the use of multi-bit flip-flops (MBFFs) has been shown to be an effective design technique to improve clock tree synthesis and can be used either as an alternative or in conjunction with the well-known clock gating approach targeting clock power reduction. The idea behind this technique is that clock tree power savings can be achieved by using flip-flop cells with optimized design and also through a reduced clock tree once the number of clock sinks is smaller in a design with MBFF cells. Some recent works have been proposing methods to take advantage of using MBFFs in standard cell based designs, where single-bit flip-flops are replaced by MBFF cells during logic and/or physical syntheses. However, a more complete analysis is still needed for different steps of a design flow to help understanding the impact of MBFFs on the physical design. We present in this work a comprehensive comparison between traditional flip-flop and MBFF implementations of an industrial 55nm design. Our results consider area, power and timing as well as some side effects like clock skew, routing congestion and voltage drop distribution. Finally, this study points to some potential drawbacks of using MBFFs which may be helpful for designers to make trade-off decisions in high performance SoC designs.