RTL functional verification using excitation and observation coverage

Code-level coverage is often used to measure RTL-level verification progress. However, a simple code-level coverage inaccurately estimates the verification result by considering only the excitations of functional blocks. A coverage measure that considers additional verification qualities, such as conditions checking or observation, can significantly extend the verification accuracy. However, identifying a design error becomes increasingly difficult as design complexity increases. This paper presents heuristic approaches that increase the chance of detecting obvious-but-easily-missed design errors by allowing a designer/verification-engineer to define additional condition states to be checked. The verification approach is implemented using Verilog Programming Language Interface (PLI) and several benchmark circuits are analyzed The results indicate a high correlation between actual error(design mutant) detection rate and the proposed coverage measure The proposed coverage enhances verification performance with less user interaction, fast coverage calculation, and with less system overhead