Optimization of GALS CMP architecture with DCT as case study

Globally Asynchronous Locally Synchronous (GALS) Chip multiprocessors with separate clocks for separate modules inside the chip are highly suited for processing number crunching and processing jobs that have to be done with limited energy. The GALS uses clock and voltage scaling jointly in system sub-modules to achieve low energy consumption rates. An advantage here is feasibility to use different clock rates for different modules in the chip. GALS allows up to 25% energy savings in addition to clock as well as voltage scalability. However, a chronic drawback of GALS is additional communication latency between the various clock domains. In addition the component processors consume power even when they are idle. Latency to a great extent is reduced by implementing large inter-processor FIFOs buffers. This work proposes to enhance the latency minimization by alternately enhance one processor domain to optimally manage latency and power wastage. Real Time System algorithms are used for managing the inter clock domain communication. This technique can be used to either enhance the FIFO buffer technique if area is not a consideration where only the efficiency is considered or as a standalone manager for handling the inter clock domain communications efficiently with reduced area and increase resource handling capability. Tri state buffers are put to use to switch clock and supply voltage to individual clock domains. For performance evaluation, Component processors to find the DCT were implemented with FIFO in between the modules for communication between processors and in turn reduce latency. Comparison of performance of the latency management processor enhanced GALS chip with FIFO buffer chip revealed increase of 15% throughput and 40% energy savings approximately as compared to 10% and 25% for the latter.