A diagnostic ATPG for delay faults based on genetic algorithms

This paper presents a GA-based technique to generate diagnostic-oriented delay tests for logic circuits. The aim is to produce a test sequence for a given circuit such that any couple of non-equivalent delay faults is distinguished by at least one rest pair belonging to the test sequence. For this purpose, we decided to preferably use a simulation-based approach with a directed search mechanism rather than developing a new deterministic ATPG. An appropriate fitness function that ranks population members according to their diagnostic capabilities has been defined, and genetic operators allowing a population to evolve during successive generations are presented. In order to have a diagnostic program providing near-optimal solutions, we combined the GA-based technique proposed in this paper with an existing post test diagnostic method for delay faults. Experimental results show that the genetic approach is effective for solving our diagnostic test generation problem, and point out the fact that the GA performs very well in comparison to a random test method