Time and Frequency Domain Modeling, Simulation, and Measurement of a Non-Standard Cabled PCI Express® Channel

PCI-Express^reg1 specifications have recently been updated to account for transmission across a cabled interface. These specifications are intended to be used with a "standard" cable, and budgeted according to the channel losses and jitter. This paper describes the design and verification of four x8 PCIe^reg channels which are neither a standard motherboard/plug-in interface, nor a standard cable interface. The channel consists of a commercially available bridge chip and an IBM ASIC driven through two printed circuit boards, two GigArray^reg High-Speed Mezzanine connectors, and a flex cable. Total channel length is roughly 25 inches (~64 cm), with nearly 15 inches in the flex cable. Standard-loss and low-loss dielectric laminates were considered for the flex cable, significant effort was spent carefully designing the flex element. A standard frequency-domain simulator was used to estimate the channel loss based on known transmission constructs in the PCBs and flex cable. Budgets were developed to the PCIe specifications and enforced with PCB and flex cable design constraints from analysis and spec requirements. Prototypes were fabricated in both standard-loss and low-loss materials, and measurements were made on both sets of hardware. A software compliance package (installed on a digital sampling oscilloscope) was used to judge the performance of the channel during system operation. Time-domain HSPICE^reg simulation was used to achieve model-to-hardware correlation, and in-situ VNA measurements were used to correlate channel loss budgets in the frequency domain. Based on measurements and analysis, the interface margin on the subsequent production pass of the hardware designs was significantly improved.