A Low Power Fast Settling CMOS S&H utilizing Auxiliary Slew Circuits

In this work new modifications to flip-around sample and hold amplifier (S&H) are presented, which improve slew rate and settling behavior of the S&H. It also results in power minimization of the OTA. Design procedure for maximum spurious free dynamic range (SFDR) and minimum power consumption of the proposed S&H is described. Using this technique, a 100 MSPS S&H with 90 dB SFDR and 4 mW power consumption is implemented in 0.18 ¿m technology. Since slewing behavior is important issue in most switched capacitor (SC) circuits, the use of the proposed method is not restricted to the flip around S&H architecture, and it can also be modified for other configurations such as gain stages.