Efficient layout editing by combining disk storage layout partitioning and cell hierarchies

This paper presents an efficient solution to the problem of dealing with the layout description of very huge chips represented by large CIF 2.0 files, and discusses how this solution is matched with the philosophy of using cell hierarchies on a VLSI layout editor. The main objectives are achieving faster disk access and attaining lower memory demands to be able to perform layout editing efficiently. This paper also presents the algorithms required to implement the functions that deal with cell hierarchies and cell instances in a hierarchical layout editor and also discusses several problems related to cell hierarchies and cell instances, such as the problem of maintaining the consistency of the project when a cell is modified