DocumentCode
2044064
Title
A floating-point validation suite for high-performance shared and distributed memory computing systems
Author
Ghoshal, S.K.
Author_Institution
Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
fYear
1997
fDate
18-21 Dec 1997
Firstpage
88
Lastpage
93
Abstract
A methodology to systematically identify and isolate bugs in floating point implementation in high performance multiple CPU computing systems is formulated. A validation suite is written and tested. Results show improper implementation. Proper implementation guidelines are suggested and prototyped
Keywords
distributed memory systems; floating point arithmetic; parallel programming; program verification; shared memory systems; distributed memory computing systems; floating point implementation; floating point validation suite; high performance multiple CPU computing systems; high performance shared memory computing systems; validation suite; Central Processing Unit; Computer bugs; Distributed computing; Error correction; Floating-point arithmetic; Hardware; High performance computing; Supercomputers; System software; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computing, 1997. Proceedings. Fourth International Conference on
Conference_Location
Bangalore
Print_ISBN
0-8186-8067-9
Type
conf
DOI
10.1109/HIPC.1997.634476
Filename
634476
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