An efficient 3D NoC synthesis by using genetic algorithms

The application of 3D Network on Chip (NoC) provides an effective way for tackling the performance bottleneck for high-performance Systems on Chips (SoCs). How to design an efficient 3D Network on Chip which is satisfied with the communication requirement of 3D system and simultaneously enables significant performance enhancements has encouraged a lot of attention. In this paper, we focus on the automatic design for custom based NoC architecture by use of a novel approach. The synthesis idea is proposed to develop a minimum cost topology and an optimized floorplan to decrease the power consumption, under the hardware and software constraints. Different algorithms are used to solve the sub-problems. In the core to switch connectivity stage, we firstly use Tarjan Algorithm to find the strong connectivity part in the core communication graph, and then use the Min-cut Algorithm to partition the core communication graph into sub-graphs. To establish the switch to switch connection, we apply Genetic Algorithm (GA) to do the path computation and flow control. Finally, we use Genetic Algorithm to solve the switch position problem. Optimized positions of switches in the floorplan for minimizing the power consumption are obtained while meeting the non-overlapping constraints. The experimental results show that our proposed synthesis approach is efficient and much power saving in the application of NoC design work.