Extension of PCI bus to 21 slots using GTLP transceiver

The PCI (peripheral component interconnect) bus in various form factors is the most frequently implemented interface for a broad class of computing application architectures in new designs. While originally developed as a local interconnect bus for the PC market (around 1994 it became the de facto standard for high speed device interconnect on PC planers), the technology has been widely adopted in both proprietary, as well as standard (CompactPCI(R) and CardBUS for example) implementations. These implementations are all limited in the number of slots supported, 4 slots in the PC and 8 slots for CompactPCI(R). This paper demonstrates how, through the application of IWS (incident wave switching) with GTLP (gunning transceiver logic plus) transceivers and an optimized backplane, the CompactPCI(R) (sometimes abbreviated to cPCI) standard can be extended to 21 slots at 33 MHz and to 14 slots at 66 MHz