DocumentCode
2051053
Title
CPLD-based system for the quadrature digital upconverter
Author
Vdovychenko, Yegor I.
Author_Institution
Ukraine Central State Designs Bur. Proton, Kharkov, Poland
fYear
2010
fDate
23-27 Feb. 2010
Firstpage
274
Lastpage
274
Abstract
In this paper CPLD-based realization of a radio technical system meant for the quadrature digital up converter control being used in the communication systems of special purpose.
Keywords
field programmable gate arrays; frequency convertors; hardware description languages; programmable logic devices; CPLD-based system; FPGA; IP-CORE design; VHDL; quadrature digital up converter control; quadrature digital upconverter; radio technical system; Clocks; Counting circuits; Debugging; Digital control; Field programmable gate arrays; Frequency conversion; Frequency synthesizers; Hardware design languages; Signal design; System testing; AD9856; AHDL; ALTERA; CPLD; IP-CORE; VHDL;
fLanguage
English
Publisher
ieee
Conference_Titel
Modern Problems of Radio Engineering, Telecommunications and Computer Science (TCSET), 2010 International Conference on
Conference_Location
Lviv-Slavske
Print_ISBN
978-966-553-875-2
Electronic_ISBN
978-966-553-901-8
Type
conf
Filename
5445928
Link To Document