The many faces of test synthesis

One of the problems of the use of the term “test synthesis” is that it is so general that almost any aspect of test automation can be claimed to fall under its umbrella. Because of the popularity of the term, and the unpopularity (particularly with CAD vendors) of having a system which does NQT carry out test synthesis, it is tempting to interpret the term as something equivalent to “synthesizing something to do with test”. Thus, an ATPG tool which automatically substitutes scan cells and connects up scan chains to a previously synthesized design can be legitimately claimed to be carrying out test synthesis. This is markedly different to a tool which inserts HDL code for BIST circuitry into the overall high level description of a design. The spirit of high level test synthesis is encapsulated in a one-pass system. Certain components are easily identifiable, for example the addition of separate circuitry like BIST controllers or TAP controllers for boundary scan. Such circuitry can be specified as HDL code and relatively easily-made to conform to design rules. For random logic, however, there needs to be a convenient way of building in necessary constraints to ensure tester-applicable patterns can be generated. To have tests which target non-stuck-at faults and which are completely automatically generated means paying attention to both additional constraints during design synthesis and better ATPG systems