Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-Chip

End-to-End Response Time Analysis (E2ERTA) can be used to examine the timing performance of a Network-on-Chip (NoC). The complexity of its calculation increases with the scaling of both the task set and core count of the NoC. This paper presents a hardware implementation of E2ERTA along with two other acceleration schemes to reduce the computation time. We explore the performance of the proposed approach, and analyse its effectiveness against the state-of-the-art in the field. The results show a significant improvement in analysing the timing performance, thus potentially enabling the use of E2ERTA as a fast and guaranteed deterministic admission controller for open and dynamic real-time systems.