A unifying methodology for intellectual property and custom logic testing

A novel direct access test methodology that unifies the testing of pre-designed intellectual property blocks and custom user designed logic is proposed. This methodology allows the test logic and wiring used for testing custom logic to be shared for testing intellectual property using pre-computed test vectors. It provides parallel access to storage elements and so alleviates some of the issues found in serial access scan techniques. It also provides a novel solution to the non-scan element state retention problem found in single edge-triggered clock based serial scan approaches