Intelligent dual-speed design for face-up chemical mechanical polishing

Chemical mechanical polishing (CMP) has become increasingly important as the feature size of the IC processing stepping into under 0.25 mum and the range of nanometers. The decreasing feature size and the increasing complexity of circuit layouts mandate the uniformity of the processing surfaces in multi-layer integrated circuits. To further improve the planarization process, the traditional face-down CMP configuration is being replaced by the face-up design for its local planarity, small form factor, and economy in material cost. In this paper, an intelligent dual-speed polishing procedure is proposed for the face-up CMP design. The integration of two different polishing speeds with parameter optimization can significantly reduce the non-uniformity of the wafer surface. Simulations are performed to demonstrate the effectiveness of the proposed dual-speed design