A scalable architecture of a structured LDPC decoder

We present a scalable decoding architecture for a certain class of structured LDPC codes. The codes are designed using a small (n, r) protograph that is replicated Z times to produce a decoding graph for a (Z×n, Z×r) code. Using this architecture, we have implemented a decoder for a (4096, 2048) LDPC code on a Xilinx Virtex-II 2000 FPGA, and achieved decoding speeds of 31 Mbps with 10 fixed iterations. The implemented message-passing algorithm uses an optimized 3-bit nonuniform quantizer that allows near floating point performance in the waterfall region, with drastically smaller hardware implementation requirements.