Examination and improvement of reading disturb characteristics of a surrounded gate STTM memory cell

Author

Ahn, S.J. ; Koh, K.H. ; Kwon, K.W. ; Baek, S.J. ; Hwang, Y.N. ; Jung, G.T. ; Jung, H.S. ; Kim, K.

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea

Volume

2

fYear

2003

fDate

12-14 Aug. 2003

Firstpage

528

Abstract

This paper introduces a novel surrounded gate STTM cell technology to improve retention and read disturb characteristics. In the memory cells previously reported, the device structures limits the CMOS-compatible memory integration and the operation voltage scaling of the memory cells. The proposed cell architecture overcomes this problem and also improves the read disturb characteristics. The proposed memory cell was fabricated using the 0.18 um design rule based on the low power SRAM process technology. This paper demonstrate an the device characteristics of the proposed memory cell and the improvement of tin a read disturb characteristics.

Keywords

CMOS memory circuits; SRAM chips; memory architecture; transistors; CMOS compatible memory integration; SRAM process; device structural limit; gate memory cell; operation voltage scaling; proposed cell architecture; read disturb characteristics; retention; scalable two transistor memory; surrounded gate STTM cell; CMOS technology; Capacitance; Consumer electronics; Nonvolatile memory; Process design; Random access memory; Research and development; Transistors; Voltage; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on

Print_ISBN

0-7803-7976-4

Type

conf

DOI

10.1109/NANO.2003.1230963

Filename

1230963