DocumentCode
2058942
Title
Performance and technology trade-offs of BiCMOS submicron processes for ASIC applications
Author
Gal, Laszlo ; Prunty, C. ; Kumar, R.
Author_Institution
UNISYS Corp., San Diego, CA, USA
fYear
1991
fDate
12-15 May 1991
Abstract
The technology trade-offs of various BiCMOS processes of submicron feature size are discussed. A method of quantifying performance, cost, density, and reliability is presented. The authors discuss the cost trade-offs and give a comprehensive performance analysis of the high-end and low-end BiCMOS processes at the 0.8-μm feature size. It is shown that a 2× performance improvement of BiCMOS over CMOS, as predicted in the literature, is not realistic for performance optimized circuits
Keywords
BIMOS integrated circuits; application specific integrated circuits; circuit reliability; integrated circuit technology; 0.8 micron; ASIC applications; BiCMOS submicron processes; performance analysis; reliability; technology tradeoff; Application specific integrated circuits; BiCMOS integrated circuits; CMOS process; CMOS technology; Costs; Integrated circuit technology; Logic arrays; MOS devices; Performance analysis; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.163993
Filename
163993
Link To Document