Pascant: a partial scan and test generation system

Author

Bhawmik, Sudipta ; Lin, Chih J. ; Cheng, Kwang-Ting ; Agrawal, Vishwani D.

Author_Institution

AT&T Bell Lab., Princeton, NJ, USA

fYear

1991

fDate

12-15 May 1991

Abstract

The authors present Pascant, a system that consists of an intelligent partial-scan flip-flop-selection algorithm and a sequential circuit test generator. The algorithm for selection of flip-flop is based on the identification and elimination of strongly connected components in a circuit graph and is shown to be more efficient than previously reported methods. An additional testability criterion based on consecutive self-loops is also presented. An overview of the Pascant system is presented with emphasis on its scan flip-flop-selection method. Test generation results for 29 of the 31 ISCAS´89 sequential benchmark circuits are given

Keywords

built-in self test; logic testing; Pascant; benchmark circuits; circuit graph; consecutive self-loops; intelligent partial-scan flip-flop-selection algorithm; overview; scan flip-flop-selection method; sequential circuit test generator; strongly connected components; test generation results; test generation system; testability criterion; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Flip-flops; Registers; Sequential analysis; Sequential circuits; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.163995

Filename

163995