DocumentCode
2059594
Title
Commercial design verification: methodology and tools
Author
Pixley, Carl ; Strader, Noel R. ; Bruce, W.C. ; Park, Jaehong ; Kaufmann, Matt ; Shultz, Kurt ; Burns, Michael ; Kumar, Jai ; Yuan, Jun ; Nguyen, Janet
Author_Institution
Adv. Design Technol., Motorola Inc., Austin, TX, USA
fYear
1996
fDate
20-25 Oct 1996
Firstpage
839
Lastpage
848
Abstract
Commercial design verification is a complex activity involving many abstraction levels (such as architectural, register transfer, gate, switch, circuit, fabrication), many different aspects of design (such as timing, speed, functional, power, reliability and manufacturability) and many different design styles (such as ASIC, full custom, semi-custom, memory, cores, and asynchronous). We present a representative design flow and methodology that is common to many commercial integrated circuit design environments and that concentrates on functional validation using informal verification (e.g., simulation, emulation and ATPG) and formal verification (e.g., logic checking and sequential verification)
Keywords
automatic testing; computational complexity; design for testability; digital simulation; formal verification; integrated circuit design; logic CAD; logic testing; random processes; ATPG; abstraction levels; commercial design verification; design flow; emulation; emulation throughput; formal verification; functional validation; informal verification; integrated circuit design environment; logic checking; sequential verification; simulation; simulation coverage; simulation monitoring; Application specific integrated circuits; Design methodology; Fabrication; Integrated circuit reliability; Integrated circuit synthesis; Manufacturing; Registers; Switches; Switching circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1996. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-3541-4
Type
conf
DOI
10.1109/TEST.1996.557145
Filename
557145
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