DocumentCode
2060022
Title
A routing testing of a VLSI massively parallel machine based on IEEE 1149.1
Author
Aktouf, C. ; Robach, C. ; Marinescu, A.
Author_Institution
LGI-IMAG, Grenoble, France
fYear
1995
fDate
21-25 Oct 1995
Firstpage
781
Lastpage
788
Abstract
A practical testing strategy is presented for locating faults occurring on both cells´ routing parts and internal physical lines within a 2D massively parallel machine. We present first an approach which does not consider all practical constraints. Then, an approach based on IEEE 1149.1 standard is studied and its efficiency is illustrated. The results obtained are given
Keywords
VLSI; automatic testing; computer testing; network routing; parallel machines; 2D massively parallel machine; IEEE 1149.1 standard; MIMD machines; VLSI; fault location; internal physical lines; routing testing; testing strategy; Circuit faults; Circuit testing; Costs; Multiprocessing systems; Parallel architectures; Parallel machines; Probes; Read-write memory; Routing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1995. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2992-9
Type
conf
DOI
10.1109/TEST.1995.529909
Filename
529909
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