Effect of via profile on copper seed layer deposition for electroplating

This paper deals with through-silicon vias (TSVs) for 3-D IC stacking, and discusses the effect of an etched via profile on copper seed layer deposition in terms of providing conformal coverage along the via sidewall. A detailed study of the uniformity of the copper seed layer deposited by a Varian XM8 magnetron sputtering system is reported. The effect of process parameters such as pressure and power on copper seed coverage is also discussed. Each parameter plays a critical role in obtaining a conformal lining of the copper seed inside the via. The copper electroplating process used to fill the vias will also be discussed. The profiles of vias under study are straight and sloped (tapered) sidewall vias with diameters of 20-25 mum.