Effect of high-κ, gate dielectrics on channel engineered deep sub-micrometer n-MOSFET device

The potential impact of high permittivity gate dielectrics on CON, and tilt angle halo implants of sub 100 nm Lateral Asymmetric Channel (LAC) n-MOSFET´s device is studied using Synopsys ISE-TCAD. In this paper, we systematically investigate the effects of the conventional, low (10deg) and high (50deg) tilt angle halo implants with different high-k gate dielectrics values for sub 100 nm lateral asymmetric channel (LAC) MOSFETs with EOT 2.5 nm. The effect in variation of gate dielectric material, on the short channel performance contributing to DIBL, I_off, I_on, Sub-threshold Swing, and I_ON/I_OFF ratio which are primarily considered as logic performance parameters of the device are studied. The same device has also been looked in for analog performance like trans-conductance (g_m) and overall gain (g_mR₀).