DocumentCode
2060567
Title
Modeling architectural improvements in superscalar processors
Author
Zhu, Y. ; Wong, W.E.
Author_Institution
Sch. of Comput., Nat. Univ. of Singapore, Singapore
Volume
1
fYear
2000
fDate
14-17 May 2000
Firstpage
28
Abstract
A model of superscalar processors using a network of Multiple-Class-Multiple-Resource queues is described and studied. In this model, we are able to model and study instruction classes, instruction dependencies, the cache, the branch unit, the decoder unit, the central instruction buffer, the functional units, the retirement buffer, the retirement unit and instruction issue policy in an integrated manner. This model has been verified against measured performance and has shown an average error of 5%.
Keywords
buffer storage; computer architecture; instruction sets; performance evaluation; queueing theory; Multiple-Class-Multiple-Resource queues; architectural improvement modeling; average error; branch unit; cache; central instruction buffer; decoder unit; functional units; instruction classes; instruction dependencies; instruction issue policy; measured performance; retirement buffer; retirement unit; superscalar processors;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing in the Asia-Pacific Region, 2000. Proceedings. The Fourth International Conference/Exhibition on
Conference_Location
Beijing, China
Print_ISBN
0-7695-0589-2
Type
conf
DOI
10.1109/HPC.2000.846511
Filename
846511
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