• DocumentCode
    2061735
  • Title

    Eliminate self-interference misses of cache through modifying data layout of arrays

  • Author

    Lu, Xinda ; Chen, Jie

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Shanghai Jiaotong Univ., China
  • Volume
    1
  • fYear
    2000
  • fDate
    14-17 May 2000
  • Firstpage
    259
  • Abstract
    Loop tiling is an effective way to improve the cache hit ratio. However, while eliminating self-interference misses, tiling may produce small tiling factors for the cases of some arrays. In order to obtain stable and proper tiling factors, a new method that automatically generates tiling factors is proposed in this paper. These tiling factors are independent of arrays and can completely eliminate self-interference misses and can also significantly reduce cross-interference misses.
  • Keywords
    arrays; cache storage; data structures; program control structures; array data layout modification; automatic tiling factor generation; cache hit ratio; cross-interference misses; loop tiling; self-interference cache miss elimination;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing in the Asia-Pacific Region, 2000. Proceedings. The Fourth International Conference/Exhibition on
  • Conference_Location
    Beijing, China
  • Print_ISBN
    0-7695-0589-2
  • Type

    conf

  • DOI
    10.1109/HPC.2000.846557
  • Filename
    846557