Low power arithmetic units using pass logic

There is a tremendous need for miniaturization as well as low power consumption in many processor architectures, especially when they are used in portable equipment. In this context, the design of low-power DSPs (digital signal processors) is of utmost importance. A clever means of achieving this is by the use of pass logic circuits in these designs, but switching activity is found to be a major contributor to dynamic power consumption. Hence, a formal technique for calculating the switching activity in CMOS pass networks is presented in this paper, which is validated using various designs of CMOS full adder cells. This technique can therefore be used for the design of CMOS pass networks with reduced switching activity, which are suitable for use in arithmetic units for the design of smaller and more energy-efficient DSPs.