8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications

Author

Myers, James ; Savanth, Anand ; Howard, David ; Gaddh, Rohan ; Prabhat, Pranay ; Flynn, David

Author_Institution

ARM, Cambridge, UK

fYear

2015

fDate

22-26 Feb. 2015

Firstpage

1

Lastpage

3

Abstract

The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses is energy efficiency, as it will prove cost-prohibitive to regularly replace billions of batteries. Node cost is another concern, which will demand ever-greater integration. Ease of SW development must also remain a priority to HW designers. Addressing all of the above, this paper presents an 11.7pJ/cycle subthreshold WSN processing sub-system implemented in low-leakage 65nm CMOS, scalable from 850nW active power at 250mV to 66MHz at 900mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80nW CPU and RAM state-retention power gating for SW-transparent leakage reduction.

Keywords

CMOS integrated circuits; Internet of Things; system-on-chip; ARM Cortex-M0+ subsystem; CMOS integrated circuit; CPU; Internet of Things; RAM state-retention power gating; SW-transparent leakage reduction; WSN; direct-battery operation; power 80 nW; size 65 nm; wireless sensor nodes; Clocks; Logic gates; Random access memory; Regulators; Solid state circuits; Switches; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid- State Circuits Conference - (ISSCC), 2015 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4799-6223-5

Type

conf

DOI

10.1109/ISSCC.2015.7062967

Filename

7062967