8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation

A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic V_M!N, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand higher voltage and performance. Alternately, a per-core fully-integrated voltage regulator (VR) provides a cost-effective means to realize autonomous DVFS [2-4]. In this paper, we present a graphics core that is supplied by a fully integrated and digitally controlled hybrid low-drop-out (LDO)/switched-capacitor voltage regulator (SCVR) with fast droop response (Fig. 8.6.1). While the LDO VR enables high power density and is area efficient, as it can use existing power headers originally employed for bypass/sleep modes, it suffers from efficiency loss at low VOUT. An SCVR, on the other hand, has improved conversion efficiency across a wide VOUT range. In an area-constrained design, however, the limited size of the SCVR´s fly capacitors and associated configurable power stages sets an upper bound on the SCVR´s maximum power density, restricting its use to lower VOUT. This LDO/SCVR combination delivers the power required by the core at a high VOUT of 0.92V with 84% LDO efficiency, while extending to a low VOUT of 0.38V with 52% SCVR efficiency from a 1.05V VIN. Compared to a shared-rail scheme, the hybrid VR enables 26% to 82% reduction in core energy versus 26% to 67% if solely the LDO is used.