• DocumentCode
    2062424
  • Title

    Double context microprocessor architecture

  • Author

    Qin, Wang

  • Author_Institution
    Dept. of Comput., Univ. of Sci. & Technol., Beijing, China
  • Volume
    1
  • fYear
    2000
  • fDate
    14-17 May 2000
  • Firstpage
    370
  • Abstract
    One of the key points for improving computer system performance is to reduce the cost of the context switch. In order to support the operating system to deal with the context switch efficiently, a double context microprocessor architecture (DCPA) is introduced. The performance of DCPA is higher than that of a single context architecture. The higher the contexts switch frequency, the bigger the difference.
  • Keywords
    computer architecture; microprocessor chips; network operating systems; processor scheduling; DCPA performance; computer system performance; context switch; double context microprocessor architecture; frequency switching; operating system; single context architecture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing in the Asia-Pacific Region, 2000. Proceedings. The Fourth International Conference/Exhibition on
  • Conference_Location
    Beijing, China
  • Print_ISBN
    0-7695-0589-2
  • Type

    conf

  • DOI
    10.1109/HPC.2000.846580
  • Filename
    846580
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2062424