On the Feasibility of Early Routing Capacitance Estimation for FPGAs

Knowing the capacitance of circuit nets in an FPGA design is essential when computing the dynamic power consumed by switching these nets. Before a circuit is placed, however, there is little information available to allow the capacitance of routing wires to be estimated. In this paper we study the feasibility of estimating routing capacitance before RTL-synthesis to allow high-level power consumption optimization algorithms to be able to target routing power. We propose a novel method for estimating the capacitance of nets before RTL-synthesis and show that this method improves the accuracy and the rank ordering of the net-by-net estimates made over existing fan-out based techniques.