L4: An FPGA-Based Accelerator for Detailed Maze Routing

This paper describes an FPGA-based accelerator for maze routing applications such as integrated circuit detailed routing. The accelerator efficiently supports multiple layers, multi-terminal nets, and rip up and reroute. By time-multiplexing multiple layers over a two-dimensional array of processing elements, this approach can support multi-layer grids large enough for detailed routing while providing at 1-2 orders of magnitude speedup over software running on a modern desktop computer. The current implementation supports a 32 times 32 routing grid with up to 16 layers in a single Xilinx XC2V6000 FPGA. Up to 64 times 64 routing grids are feasible in larger commercially available FPGAs. Performance measurements (including interface overhead) show a speedup of 29X-93X over the classic Lee Algorithm and 5X-19X over the A* Algorithm. An improved interface design could yield significantly larger speedups.