A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors

Several optimization strategies for cache design in embedded bus-based symmetric multiprocessor are proposed in this paper. To reduce the miss penalty of the cache, optimized MESI snoopy protocol and pipelined split-transition bus architecture as well as snoopy filter mechanism are applied in the proposed design. With these strategies, transactions on the bus along with memory accesses and unnecessary snoopy actions also decrease remarkably, which will save a large part of the power consumption. The proposed design is implemented in IMS-DPU SoC chip by CSMC 180nm technology with a clock frequency of 100MHz and 158.4K equivalent logic gates (including 4KB memory).